Department organized a one day workshop on “FPGA Design using Xilinx”. VLSI Design System using VHDL or VERILOG was conceptualized by some top industry professionals in association with DKOP Labs Pvt. Ltd.
The workshop was conducted in Multimedia Centre of the University on 08/04/2015.
Chairman, Dr. Munish Vashishath addressed the participants on the occasion and asked the students to be prepared for professional challenges ahead.
The workshop was coordinated by Dr. Pradeep Kumar.